上海交通大学.计算机体系结构.研究生课件方案.pptx

Advanced Computer ArchitectureLecture 5, Spring, 2016ZHU Yongxin, Winson zhuyongxin@sjtu.edu.cn;Outline;Instruction Set ArchitecturesPart 1;The confusing classifications;1ST Successful ISA;IBM 360;IBM 360;IBM 360 architecture;Relevant Classic Papers Debating ISA;Some concluding remarks on ISA;Many ways to classify ISAs;Running examples;What’s going on??;Instruction Length;Instruction Length;Intel variable instruction length;Intel SSE4 Instrutions;Intel Virtualization Instructions;Microcode;How many registers? ;How many registers? ;Classifying ISA in the textbook;Where do operands reside? ;Load-store architectures;Memory operands and total operands of ISAs;Comparing the Number of Instructions;Why are register (load/store) architectures hot?;Endianness interpretations;Endianness examples;Endianness examples;CPU Endianness;Endianness also applicable to some files;Alignment interpretation;Alignment interpretation;Alignment examples;Alignment examples;Outline;Addressing modes;Register, Immediate;Displacement;Register indirect, Indexed;Direct, Memory Indirect;Autoincrement, Autodecrement;Scaled;Frequency of address modes;Distribution of displacement modes;Distribution of immediate addressing modes;Concluding remarks on addressing modes; ARM Instruction Set;The Conditional Field;Some Unique Features of ARM;Some Unique Features of ARM;Some Unique Features of ARM;Outline;Example: MIPS (- MIPS);;Approaching an ISA;Outline;;5 Steps of MIPS DatapathFigure A.3, Page A-9;Inst. Set Processor Controller;5 Steps of MIPS DatapathFigure A.3, Page A-9;Visualizing PipeliningFigure A.2, Page A-8;Pipelining is not quite that easy!;One Memory Port/Structural HazardsFigure A.4, Page A-14;One Memory Port/Structural Hazards(Similar to Figure A.5, Page A-15);; Read After Write (RAW) InstrJ tries to read operand before InstrI writes it  Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication.;Write After Read (WAR) I