soc设计方法与实现第4章架构设计.pptVIP

第四章 SoC架构设计及ESL设计 Outlines System design Commonly used cores and buses What Why ESL design ESL design Methodology ESL design stages Transaction Level Modeling and standard What ESL design tool do Summary Example of Hardware System Architecture SoC design includes System architecture design Software structure design Hardware design (chip design) Key system Architecture Questions Application analysis Which processor should I choose? Hardware/Software partitioning What is in hardware, what is in software? Bus and memory architecture How do I implement the control stream? How do I implement the data stream? Commonly Used Cores DSPs ARM（Advanced RISC Machines) RISC architecture ARM7, ARM9, ARM10, ARM11 MIPS (Microprocessor without interlocked piped stages) RISC architecture MIPS 32, MIPS 64 PowerPC (Developed by IBM、Motorola、Apple) TI’s DSP TMS320C54, TMS320C55, TMS320C62,TMS320C64 ADI’s DSP ADSP-21, SHARC, TigerSHARC, Blackfin Freescale’s DSP DSP56300, StarCore Commonly Used Buses ARM’s AMBA Commonly Used Buses – cont. IBM’s CoreConnect Commonly Used Buses – cont. Silicore’s Wishbone 4 kind of interconnections: Point-to-point, data flow, shared bus, crossbar switch OCP (Open Core Protocol) Bus Avalon Bus Developed by Altera for Nios core on FPGA Multi-processor SoC (MPSoC) TI’s DaVinci: ARM+DSP Block diagram of TMS320DM6446/3 for multimedia application MPSoC – cont. TI’s DaVinci : Source sharing and communication between two cores Outlines System design Commonly used cores and buses What Why ESL design ESL design Methodology ESL design stages Transaction Level Modeling and standard What ESL design tool do Summary System level Design Challenges How do I understand performance of key IP blocks before designing? System-on-Chip does not mean to simply put IP into a chip How to build an optimized system? A system means software + hardware Complexity Drive ESL Design 90nm SoC Two or three of microprocessors and more DSPs Considerably more memory