用在HCL中表示指令.ppt

SEQ CPU Implementation What we will discuss today? The implementation of a sequential CPU ---- SEQ Every Instruction finished in one cycle. Instruction executes in sequential No two instruction execute in parallel or overlap An revised version of SEQ ---- SEQ+ Modify the PC Update stage of SEQ to show the difference between ISA and implementation Some Macros SEQ Hardware Structure Stages Fetch Read instruction from memory Decode Read program registers Execute Compute value or address Memory Read or write data Write Back Write program registers PC Update program counter Instruction Flow Read instruction at address specified by PC Process through stages Update program counter Difference between semantics and implementation ISA Every stage may update some states, these updates occur sequentially SEQ All the state update operations occur simultaneously at clock rising (except CC) SEQ Hardware Key Blue boxes: predesigned hardware blocks E.g., memories, ALU Gray boxes: control logic Describe in HCL White ovals: labels for signals Thick lines: 32-bit word values Thin lines: 4-8 bit values Dotted lines: 1-bit values Fetch Logic Predefined Blocks PC: Register containing PC Instruction memory: Read 6 bytes (PC to PC+5) Split: Divide instruction byte into icode and ifun Align: Get fields for rA, rB, and valC Fetch Logic Control Logic Instr. Valid: Is this instruction valid? Need regids: Does this instruction have a register bytes? Need valC: Does this instruction have a constant word? Fetch Control Logic Decode Write-Back Logic Register File Read ports A, B Write ports E, M Addresses are register IDs or 8 (no access) A Source E Destination Execute Logic Units ALU Implements 4 required functions Generates condition code values CC Register with 3 condition code bits bcond Computes branch flag Control Logic Set CC: Should condition code register be loaded? ALU A: Input A to A