AMBA总线bus介绍.ppt

* 例：DMA Step0：CPU检查DMA的状态以确认是否可用 While(1) { Read(0x30004,status) if(status == 0) break; } * 例：DMA Step1：CPU设置（source address）、（destination address）（size） Write (0x30008,0x10000) Write(0x3000C,0x20000) Write(0x30010,0x100) Step 2: 启动DMA Write(0x30000,0x1) * 例：DMA Step3： DMA把数据从memory 1 传送到memory 2 * 例：DMA Step 4：DMA 向CPU发出中断请求 Step 5：CPU检查DMA的状态 Read(0x30004, status) * All systems require some master to be granted at any time. If no master is requesting then you should grant a master by default. However there are two types of “default” master. The first is a simple dummy master which only performs IDLE cycles. This master never does anything useful with the bus. The second is a default master which is a real master. This master will again perform IDLE cycles until either another master requests or it actually wants to use the bus. The advantage with this master is that if it needs the bus it does not have to go through the 2 cycle arbitration period. However in systems that support SPLIT operations we have the possibility of all masters receiving SPLIT responses. The only safe master to grant in this case would be a full dummy master. If a locked access gets a split response then all you can legitimately grant is the dummy master as lock means grant no other master combined with split meaning grant another master. * With a 32 bit address bus we can address 4Gb of address space. It is unlikely that a design will fully utilise this space so 2 options are left. The simplest is to continuously address the available slaves (wrapping round ignoring the MSBs of the address) but this risks missing why the code has exceeded its available real memory space. It also may leave gaps. The standard solution is to define a default slave which is selected in all places where no real slave exists. This will trap both gaps in the memory map and when software exceeds the physical limits of available memory. The response given by this default slave depends on the