处理器数据通道和控制器.ppt

Lecture 6 Datapath and Controller Peng Liu liupeng@zju.edu.cn Review: MIPS Storage Layout Procedure Activation Record (Frame) Each procedure creates an activation record on the stack Review: Register Assignments Calling Convention Caller vs. Callee Saved Registers Preserved registers (Callee Save) Save register values on stack prior to use Restore registers before return Not preserved registers (Caller Save) Do what you please and expect callees to do likewise Should be saved by the caller if needed after procedure call Review: Critical Timing Issues Flops work great as long as input is stable when clock rises Called setup and hold windows Clock skew can cause some nasty problems Hold time violations Cycle Time = longest Prop Delay + Setup + Clock Skew Review: How to Execute Instructions First we need to: Fetch the instruction Then we need to: Decode instruction/fetch register Then we need to: Do the operation Then we need to: Write the result into register file Finally we need to: Calculate the next instruction address Review: Memories In Our Design They will be combinational Otherwise we can’t complete an instruction in one cycle! Interface is simple: Inputs: Address DataIn WriteEn (WriteEn must be a pulse) Outputs: Dataout Register file: It has three address, two for reads, and one for write It is called a 3-port, since it can perform 3 accesses per cycle Instruction Fetch Register to Register Operations In our subset this is only addu and subu I do not want to worry about overflow addu rd, rs, rt subu rd, rs, rt Operation R[rd] - R[rs] + R[rt]; Add operation R[rd] - R[rs] - R[rt]; Sub operation OR Immediate RTL OR Immediate instruction ori rt, rs, imm R[rt] - R[rs] OR ZeroExt(imm); Means I need to get instr[15:0] into the datapath, on RT path Datapath: Immediate Ops Extend datapath to support immediate operations Write register is rt or rd based on instruction Read data 2 is ignored for immediates Immediates can be sign or zero extended