NIOS_II_各种性能表格.pdfVIP

Nios II Performance Benchmarks 2015.02.25 DS- Subscribe Send Feedback Performance Benchmarks Overview ® This datasheet lists the performance and logic element (LE) usage for the Nios II Classic and Nios II Gen2 soft processor, and peripherals. Nios II is configurable and designed for implementation in Altera® FPGAs. The following Nios II processors cores were used for these benchmarks: • Nios II/f—The Nios II/f “fast” processor is designed for high performance while presenting the most configuration options which are unavailable in the other Nios II processors. • Nios II/s—The Nios II/s “standard” processor is designed for small size while maintaining moderate performance.(1) • Nios II/e—The Nios II/e “economy” processor is designed for the smallest possible processor size while providing adequate performance. The default options for the Nios II processor were chosen for these benchmarks, unless specified otherwise. ® Note: Results may vary slightly depending on the version of the Quartus II software, the version of the Nios II processor, and the target device. Also, any changes to the system logic design might change the performance and LE usage. All results are generated using Qsys-based designs; Thef max for Nios II Classic/Gen2 Processor System (MHz) and MIPS for Nios II Classic/Gen2 Processor System tables list the fmax and millions o