资料 Single Event Effects in FPGA Devices 2014-2015.pdf

/search.jsp?R=20150015964 2018-09-11T09:24:54+00:00Z Single Event Effects in FPGA Devices 2014-2015 Melanie Berg, AS&D Inc. in support of the NEPP Program and NASA/GSFC Melanie.D.Berg@NASA.gov Kenneth LaBel: NASA/GSFC Jonathan Pellish: NASA/GSFC To be presented by Melanie Berg at the NASA Electronic Parts and Packaging Program (NEPP) Electronics Technology Workshop (ETW), NASA Goddard Space Flight Center in Greenbelt, MD, June 23-26, 2015. Acronyms • Block random access memory (BRAM) • Operational frequency (fs) • Built-in-self-test (BIST) • Processor (PC) • Combinatorial logic (CL) • Phase locked loop (PLL) • Commercial off the shelf (COTS) • Power on reset (POR) • Complementary metal-oxide • Probability of flip-flop upset (PDFFSEU) semiconductor (CMOS) • Probability of logic masking (Plogic) • Device under test (DUT) • Probability of transient generation (Pgen) • Digital Signal Processing Block (DSP) • Probability of transient propagation (Pprop) • Distributed triple modular redundancy • Radiation Effects and Analysis Group (DTMR) (REAG) • Edge-triggered flip-flops (DFFs) • Single event functional interrupt (SEFI) • Field programmable gate array (FPGA) • Single event latch-up (SEL) • Global triple modular redundancy • Single event transient (SET) (GTMR)