基于ASIC实现的半定制FIFO设计（毕业学术论文设计）.docVIP

摘要 河南科技大学本科毕业设计（论文） PAGE IV PAGE IV 基于ASIC实现的半定制FIFO设计 摘 要 绝大部分ASIC设计工程师在实际工作中都会遇到多时钟域设计的问题，多时钟域设计的一个难题是如何避免亚稳态的产生。异步FIFO是一种不同时钟域之间传递数据的常用方法。避免亚稳态问题及空满控制信号的产生是异步FIFO设计的两个关键。本文针对异步时序产生的问题提出了一种新的异步FIFO设计方案。用这样一个异步FIFO模块实现FPGA内部不同时钟系统之间的数据接口，它们之间不需要互相握手，只需跟接口FIFO模块进行交互就可以了，使设计变得非常简单和容易。该实现方案,运用整体移位实现数据正确写入和输出,使用缓冲寄存器组存放移位产生的多余数据,适用于频率不成整数倍的异步时钟域之间的数据传输. 利用串联的D触发器作为同步器,避免产生亚稳态,实现异步信号的同步. 采用自顶向下的半定制ASIC ( Application Specific Integrated Circuit)流程对其进行设计:使用Verilog硬件描述语言,利用Modelsim进行时序和功能仿真、Synopsys DC完成逻辑综合、Astro实现自动布局布线，通过对设计进行简单的修改，即可用于各种不同的系统的设计，经过充分测试和优化，该异步FIFO运行稳定，占用FPGA内部资源也非常少。将该方案与传统的异步FIFO实现方案进行比较,面积大约缩小一半,工作速度提高约三分之一。 关键词：多时钟域，异步FIF， ASIC，整体移位，缓冲寄存器组 ASIC Design of a Novel Structure Asynchronous FIFO ABSTRACT Most of the ASIC’s ever designed are driven by multiple asynchronous clocks. An important problem in multi-clock domain design is how to avoid metastability. Asynchronous FIFO is a general way to communicate between different clock domains. Metastability and how to generate empty and full flag correctly is key in the design of asynchronous FIFO. Aiming at the issue of asynchronous design, this paper proposes a new method to overcome these problems. It uses the asynchronous FIFO to interface between clock systems inside FPGA, and there is no need to shake hand with the other clock system. In this method the interface becomes very easy and also stable, and the two sides operate inside its own clock system.In this scheme,unitary shift is used to realize data`s correct read—in and output,and buffers are used to store the left data of unitary shift.This design is applicable for data transmission between clocks not integralmultiple.Synchronizer of Dtriggers in series is used to avoid instability and synchronize asynchronous signals.This circuit is designed with semicustom ASIC(Application Specific Integrated Circuit) flow which is based on top-down flow.The design uses Verilog hardware language,adopts and Modelsim to simulate , Synopsys DC to realize logic s