毕业论文设计《基于CPLD数字电压表设计》.doc

摘 要 本论文介绍了应用硬件描述语言（VHDL）来进行数字电压表的设计过程。主要介绍了使用它来设计数字系统硬件电路的方法。使设计人员摆脱传统得人工设计方法的框框，使数字系统设计的水平上升到一个新阶段。VHDL语言是一种面向设计的多层次、多领域且得到一致认同的标准硬件描述语言。它具有两大优点： 支持自上而下的TTD设计。它直接面向用户，从系统的总体要求出发，根据电路系统的行为和功能要求，自上到下逐层的完成了相应的设计描述、综合与优化、模拟与验证，直到最终生成器件，从而完成系统的整体设计。 大大缩短了逻辑电路的设计周期。论文详细介绍了（A/D转换器、二—十进制的转换、十进制—BCD码的转换、多路数据选择器、数码管的显示等程序设计），为使系统设计的更加科学合理，并在编程之后，对主要参数进行了详细得计算；论文还介绍了使用MAX PLUS II软件，另外还附了异步加法器。在论文最后还附有参考文献、外文资料，及译文。 关键词： 硬件描述语言（VHDL）、模数转换（A/D）、MAX PLUS II、复杂可编程控制器件（CPLD） Abstract Using a hardware description language—VHDL to design a voltage watch，is introduced in this paper.Emphatically,the method which we make use of VHDL to designing restrictions,and will make an epoch in the design of digital systems which will attain a higher level. VHDL is a hardware deseription language that faces design , and appropbated by general consensus. There are two advantageous factors in using VHDL: Supporting superincumbent TTD design. VHDL faces users directly, and users can design from the entire request according to the action and function of circuit systems. Using VHDL, the user can gradually accomplish the task by steps, starting from the design’s description , then synthesis and optimization、simulation and test, till creating logic elements finally. Ultimately, the entire design is completed. Cuting the period of the design short greatly. The paper introduces (A/D ZHUANHUANQI、SHI—BCD 码的转换、多路数据选择器、数码管的显示)in detail. And also introduces the application of software MAX PLUS 2.in addition, asynchronous adder is appended in the paper. And at the rear of this paper, reference literature, foreign language files and translation are added. In order to make the design more reasonable, we compute the main parameters in detail after the procedure. KeyWords: VHSIC Hardware Description Language Model Digital Convert Organon Multiple away matrix and programmable logic user system Complex Programmable Logic Device 目录 引言…………………………………………………………… （4） CPLD的概述…………………………………………………… (5) 可编程逻辑器件的发展历程