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MIPI__协议详细介绍.ppt

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MIPI__协议详细介绍.ppt

DSI Layers Outline D-PHY Introduction Lane Module, State and Line levels Operating Modes Escape Mode System Power States Electrical Characteristics Summary Introduction for D-PHY D-PHY describes a source synchronous, high speed, low power, low cost PHY A PHY configuration contains A Clock Lane One or more Data Lanes Three main lane types Unidirectional Clock Lane Unidirectional Data Lane Bi-directional Data Lane Transmission Mode Low-Power signaling mode for control purpose:10MHz (max) High-Speed signaling mode for fast-data traffic:80Mbps ~ 1Gbps per Lane D-PHY low-level protocol specifies a minimum data unit of one byte A transmitter shall send data LSB first, MSB last. D-PHY suited for mobile applications DSI:Display Serial Interface A clock lane, One to four data lanes. CSI:Camera Serial Interface Two Data Lane PHY Configuration Lane Module PHY consists of D-PHY (Lane Module) D-PHY may contain Low-Power Transmitter (LP-TX) Low-Power Receiver (LP-RX) High-Speed Transmitter (HS-TX) High-Speed Receiver (HS-RX) Low-Power Contention Detector (LP-CD) Three main lane types Unidirectional Clock Lane Master:HS-TX, LP-TX Slave:HS-RX, LP-RX Unidirectional Data Lane Master:HS-TX, LP-TX Slave:HS-RX, LP-RX Bi-directional Data Lane Master, Slave:HS-TX, HS-RX,LP-TX, LP-RX, LP-CD Universal Lane Module Architecture Lane States and Line Levels The two LP-TX’s drive the two Lines of a Lane independently and single-ended. Four possible Low-Power Lane states (LP-00, LP-01, LP-10, LP-11) A HS-TX drives the Lane differentially. Two possible High Speed Lane states (HS-0, HS-1) During HS transmission the LP Receivers observe LP-00 on the Lines Line Levels (typical) LP:0~1.2V HS:100~300mV (Swing:200mV) Lane States LP-00, LP-01, LP-10, LP-11 HS-0, HS-1 Operating Modes There are three operating modes in Data Lane Escape mode, High-Speed (Burst) mode and Control mode Possible events starting from the Stop State of control mode Escape mode request (LP-11→LP-10→LP-00→LP-01→LP-00) High-Spee

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