多核网络处理器片上总线的设计与验证-集成电路工程专业论文.docxVIP

摘要 摘要 摘 要 为了满足现代网络处理器的性能需求，本文为新一代西电网络处理器（Xidian Network Processor,XDNP）设计了一组高带宽，并行性好的片上总线，并根据数据 信息传输特点，采用了不同的总线结构，实现了性能和资源的良好折中。 在设计实现阶段，将 XDNP 片上总线的结构分为了命令总线部分和数据总线 部分。命令总线部分根据目标单元的类型采用了多层总线和共享总线相结合的结 构，数据总线部分则根据数据传输量的特点分为了 SRAM 数据总线和 DRAM 数据 总线，其中 SRAM PUSH 数据总线、SRAM PULL 数据总线、DRAM PULL 数据 总线采用了交叉开关的总线结构，DRAM PUSH 数据总线则采用了多层总线和共 享总线相结合的总线结构。XDNP 片上总线上的仲裁器以固定优先级算法和轮转 优先级算法为基础根据通信特点采用不同的仲裁策略，有效地保证了请求的优先 性和公平性，FIFO 缓存则保证了系统的并行性。 在设计验证阶段，以 VMM 验证方法学为指导，为 XDNP 片上总线搭建了测 试平台，分别统计了功能覆盖率、断言覆盖率、代码覆盖率并验证了数据的完整 性，从而全面证明了设计的正确性。利用 Design Compiler 在 SMIC 0.13um 工艺下 对 XDNP 片上总线进行了综合，综合频率为 400MHZ，系统理论带宽为 175Gbps， 最后对数据传输时间进行了统计分析，证明了片上总线良好的实时性和并行性。 关键词：多核网络处理器 交叉开关 VMM 验证方法学 Ab Abstract Abstract In this paper,a set of on-chip bus with large throughput and good parallelism is designed for the new generation of Xidian Network Processor to meet the performance requirements of the modern network processor.This design contains different bus structures according to the characteristics of data transmission and it also achieves a well trade-off between resource and performance. In the implementation stage,the on-chip bus of XDNP is divided into command bus and data bus.According to the type of the target unit,the architecture of command bus is a combination of the multi-layer bus and the shared bus.the data bus is divided into the SRAM data bus and DRAM data bus according to the amount of data transmission.The crossbar switch bus structure is design for the SRAM PUSH data bus and the SRAM PULL data bus and the DRAM PULL data bus.The combination bus architecture of the multi-layer bus and the shared bus is designed for DRAM PUSH data bus.The arbitration policies of the arbiters in the XDNP on-chip bus vary with the communication characteristics to guarantee the priority and the fairness of the requests.The FIFOs guarantee the parallelism of the system. In the verification stage, a test platform based on the VMM methodology is built to get the functional coverage, assertion coverage and