AVC编码器中运动估计的低代价VLSI实现.pdfVIP

北京大学学报 ( 自然科学版), 第 50 卷 , 第 4 期 , 2014 年 7 月 Acta Scientiarum Naturalium Universitatis Pekinensis, Vol. 50, No. 4 (July 2014) doi: 10.13209/j.0479-8023.2014.133 Low-Cost VLSI Implementation of Motion Estimation for H.264/AVC Encoders 1 1,† 1 2 WANG Teng , WANG Xin’an , XIE Zheng , HU Ziyi 1. Key Lab of Integrated Micro-Systems, Shenzhen Graduate School of Peking University, Shenzhen 518055; 2. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029; † Corresponding author, E-mail: anxinwang@pku.edu.cn Abstract A pipelined architecture with novel memory structure is proposed with several modifications of the ME algorithm. Fast motion estimation with low hardware cost and less memory access is achieved by proper search strategy, efficient rate distortion optimization (RDO) cost calculation and interpolation components, innovative memory structure and optimized dataflow scheduling. The proposed design is synthesized by SMIC 130 nm CMOS technology process with a clock frequency of 167 MHz and consumes 181.7 K logic gates and 13.8 KB memory, which shows great hardware efficiency compared with other designs. The proposed design was finally integrated within an H.264/AVC encoder for FPGA prototyping and VLSI implementation. The core area of the overall chip is 1.74 mm×1.74 mm with SMIC 65 nm CMOS technology which can support real-time HD(1080P@60fps) encoding with a clock frequency of 350 MHz. Key words H.264/AVC; motion estimation; pipeline architecture; real-time HD encoding; VLSI implementation H.264/AVC 编码器中运动估计的低代价VLSI 实现