基于调试异常模型的嵌入式处理器片上调试设计-浙江大学.PDF

446 浙 江 大 学 学 报 () Vol.44 o. 6 20106 Journal of Zhejiang U niversity (Engineering Science) June 2010 DOI: 10. 3785/j.issn. 1008973X.2010.06. 003 1 1 1, 2 1 刘 鹏, 钟 耿 , 徐国柱 , 邬可俊 ( 1. , 310027; 2. , 310012) : , , JTAG(joint test action group) , JT AG . RISC32E , ,, ., . : ;JTAG; ; : TP 316 : A : 1008973X( 2010 Onchip debug design based on debug exception model for embedded processor 1 1 1,2 1 LIU Peng , ZHO G Geng , XU Guozhu , WU Kejun ( 1. D ep ar tment of I nf or mat ion Sc ience and E lectr onic E ng ineering , Zhej iang Un iv er sity , H angz hou 310027, Ch ina; 2 H angz hou S ilan M icr oelectro nics CO , L T D, H angz hou 310012, Ch ina ) Abstract: A general precise debug exception model based on pipeline was established with portability, which provides a strategy for onchip debug by adding generation and processing mechanism of precise debug exceptions, such as debug interrupt, step, hardware/ software breakpoints, etc., in addition of a segment of offchip debug memory and a fast transfer method through joint test action group( JTAG) port. The implementation of the proposed model on an embedded processor RISC32E shows that it meets the requirements of observability and controllability. The above description should not be taken as limiting the utilization of the model which is defined by the sixpipeline microprocessor. The model can be easily transplanted onto other microprocessors which havevarious modifications of pipeline. Theproposed strategy has great efficiency of debugging in the case of comparison of some basic debugging operation