基于SOPC的RSA算法的IP核设计-集成电路工程专业论文.docxVIP

基于SOPC的RSA算法的IP核设计-集成电路工程专业论文.docx

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基于SOPC的RSA算法的IP核设计-集成电路工程专业论文

Abstract With the rapid development of modern information technology, information security problems have became increasingly prominent, and have been widespread concern in all aspects of society. RSA algorithm is not only used for both message encryption, but also be used for digital signatures, authentication, so in the field of security or authentication it is widely used. As the RSA algorithm is very high computational complexity of cryptographic algorithms, hardware implementation of the RSA is very difficult, that will need a lot of logic gates and circuit area is quite large, practicality is poor. The use of software to achieve RSA, computing speed is too slow and achieve efficiency is very low, but also that reduces the intensity of anti-decryption. The SOPC system can solve the pure software and pure hardware implementation deficiencies and shortcomings, therefore, this paper designed a based on SOPC RSA algorithm IP core. That is to say: the use of a combination of hardware and software methods to implement the RSA algorithm, is to find the best combination between speed of operation and circuit resources and to get a better performance. This paper introduces the subject of background, research status, SOPC technology, IP core technology and the basics of the RSA algorithm and the algorithm works. And in-depth study of the RSA algorithm implementation is proposed based on SOPC system design. In the overall design ,system is divided into two parts, one part of the software: generate the key pair, as in the encryption and decryption process this part is executed only once, so the use of software, will not affect the operation speed, and reduces the circuit resources. Second, the hardware: As modular exponentiation is the core of the RSA algorithm, which directly affects the operation speed encryption and decryption speed, so this part is implemented in hardware. This paper details the implementation of modular exponentiation various sub-modules, and commun

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