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具有绝缘柱结构的双栅mo们sfet的性能研究-微电子学与固体电子学专业毕业论文
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Abstract
In recent years,with the rapid development of electronic industry,the requirements of chip integration and performance of miniaturization MOS device become more and more higher.After the device size goes into nanometer level, various kinds of negative phenomena appear which will affect the performance of device directly indirectly.In order to alleviate the impact of these problems the device,the lutions be list follows:First,to fmd new device structures and
new material preparation process;Second,to new manufacturing process techno logy;Last,to find the theoretical model which bring better performance. This paper the fust solution to study new structure called DPDG(Dielectric Pocket Double Gate)MOSFET.It bases the structure of double gate MOSFET, which add DP at the edge of and drain region.With DP structure,the shared
charge between source、drain and channel becomes weaken,breakdown characteristics and the control capability of the gate are improved and short-channel effects(SCE)is suppressed。Therefore,it is more suitable for high temperature environment and the reliability of the device is improved.DPDG MOSFET becomes more and more popular in small devices and it has became of the best candidates in the nanometer CMOS circuits design with high-temperature.
Based the DPDG MOSFET device structure,electrical characteristics in channel simulated through the simulation software Atlas in this paper.Body
potential and the electric field of DPDG MOSFET and DG MOSFET also
simulated.It is found that the potential and electric field at the surface of the insulating column in the source-drain channel reduce greatly.Thus,DPDG MOSFET has more advantages to suppress Hot Carrier Effects(HCE)and SCE.The carrier mobility in the channel center,Id~Vds characteristics and Id~Vgs characteristics are also simulated.Finally,sub—threshold voltage(Vt),sub-threshold slope(ss),drain
induced barrier lowering(DIBL)at different channel length analyzed.The results
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