基于UVM的Preamp芯片的验证与分析-软件工程专业论文.docxVIP

摘 要 在集成电路迅速发展的今天，RTL 设计的复杂度不断增加，验证的难度也明 显增大，传统的验证方法以及流程已经不能满足集成电路验证要求，如何提高验 证效率和质量已经成为重中之重。 本文的工作重心是针对 Preamp 芯片中 Writer 数字模块搭建验证平台并验证其 功能，提出使用重用性更强的 UVM 验证策略。通过分析 Writer 的功能及其规格说 明，得到包括：SPI 时序，Writer Control，Writer Latch 等模块的待测功能点共 24 点 。 随后， 应用 UVM 开发出 施加 激励的 Sequence 机 制 ， 从 针 对 寄 存 器 的 op_sequence 到描述 Testcase 的 app_sequence 共 65 条，并配合 Sequence 机制开发 出方便功能覆盖率收集的 RGM 模型。 对于模块的验证，通过可回归性测试应用断言定位 RTL 的错误。为了确保对 模块做了完备的验证，验证流程采用了带有断言并集合功能覆盖率的验证流程。 项目中一共开发出测试激励 15 条，断言语句 86 条。最终的条件，语句，跳转等 覆盖率达到 99.8%，同时功能覆盖率达到 100%。 此外，本文还介绍了应用 UVM 相关机制搭建平台的策略以及新的验证流程， 这种方法已经成功的应用到项目当中，在保证了芯片质量的基础上提高了验证效 率。 关键字：Preamp 芯片 SystemVerilog UVM 功能覆盖率 断言   Abstract With the fast development of Integrated Circuit, the complexity of the RTL design has increased,so the hardness of the verification has also increased.The traditional verification mothedology and its flow can not fulfill the requirement of the new design,so how to improve the efficiency and quality has becoming more and more important. This paper’s key point is building the testbench for the Writer digital module of the preamp chip and verify its function,proposing applying the more reusable UVM methodology.Next,analyse the specification to find out 24 verification points,including SPI timing,Writer Control,Writer Latch and so on.Then developing the Sequence mechanism which trigger the DUV using UVM,from the op_sequence which describe the register to utter app_sequence which describe the Testcase.Then develop the RGM model combining the Sequence mechanism. To the verification of the Writer,using the assertions to locate the RTL bugs in the regression result.In order to guarantee the complete verification of the module, the functional coverage based with the assertions verification flow is applied .In the project,the author create 86 assertions and 15 testcases and final code coverage reach 99.5%,meanwhile the functional coverage reach 100%. This paper introduced the strategy that how to build a complete verification e