18～27GHz可调谐八波段时分LTE多模接收机前端分析与设计.pdfVIP

Vol. 32,No. 5 JournalofSemiconductors May2011 Analysisanddesignofa1.8–2.7GHztunable8-bandTDDLTEreceiverfront-end WangXiao(王肖),WangYuji(王玉吉),WangWeiwei(王伟威),Chang Xuegui(常学贵), YanNa(闫娜) ,TanXi(谈熙),and Min Hao(闵昊) State Key Laboratory of ASIC System, Fudan University,Shanghai 200433,China Abstract: This paper describes the analysis and design of a 0.13 m CMOS tunable receiver front-end that sup- ports8TDDLTEbands,coveringthe1.8–2.7GHzfrequencybandandsupportingthe5/10/15/20MHzbandwidth and QPSK/16QAM/64QAM modulation schemes. The novel zero-IF receiver core consists of a tunable narrow- band variable gain low-noise amplifier (LNA), a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier, an LO divider, a rough gain step variable gain pre-amplifier, a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier. The LNA can be tuned by reconfiguring the output parallel LC tank to the re- sponding frequency band, eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes. The test chip is implemented in an SMIC 0.13 m 1P8M CMOS process. The full receiver achieves 4.6 dB NF, –14.5 dBm out of band IIP3, 30–94dBgainrange and consumes 54 mA with a 1.2 V power supply. Keywords: long-termevolution; receiver; tunable; CMOS DOI: 10.1088/16