08～09数字逻辑期末考试试卷评讲.pptVIP

4. If use the simplest state assignment method for 133 states，then need at least[ ]state variables。 5. If number [ A ] two’s-complement and [ B] two’s-complement, calculate [-A-B ] two’s-complement, [-A+B ] two’s-complement and indicate whether or not overflow occurs. [-A-B ] two’s-complement= [ ], overflow: [ ] [-A+B ] two’s-complement=[ ], overflow: [ ] 6. One state transition equation is Q*=JQ’+K’Q。If we use D flip-flop to complete the equation，the D input terminal of D flip-flop should be have the function D=[ ]。 三. Try to finish logical function F(W,X,Y,Z) = ∑wxyz（3,6,7,10,11,14）by one chip of 74X138 and one 8-input nand gate .[10 ] 解： F(W,X,Y,Z) = ∑ WXYZ（3,6,7,10,11,14） = W’X’YZ+ W’XYZ’+ W’XYZ+ WX’YZ’+ WX’YZ+ WXYZ’ =Y（W’X’ Z+ W’XZ’+ W’XZ+ WX’Z’+ WX’Z+ WXZ’） = Y·∑WXZ（1,2,3,4,5,6） 2. The excitation/output table of a clocked synchronous state machine using D flip-flops shown as follow，Write the excitation equations and output equation. [9] K-map for Z 六. Clocked Synchronous State Machine Analysis [ 15 ] 1. Analyze the circuit of a clocked synchronous state machine shown below, write the excitation equations, output equation, transition equations and construct a transition/output table. [10] 解：output equation :MAX=EN·Q1·Q0 the excitation equations: D0=EN’·Q0+EN·Q0’=EN⊕Q0 D1= EN’·Q1+EN·Q0’ Q1+ EN·Q0 Q1’ transition equations: Q0*=EN’·Q0+EN·Q0’=EN⊕Q0 Q1*= EN’·Q1+EN·Q0’ Q1+ EN·Q0 Q1’ 2. The transition equations and output equitation of a clocked synchronous state machine is shown as follows. Complete the timing diagram for Q1,Q0 and Y, assuming that the machine starts in state Q1,Q0=00 and flip-flops are positive-edge-triggered. [5] transition equations：Q0*=Q0A’+Q1’A Q1*=Q1’+Q1’Q0A+Q1Q0’A output equitation: Y=Q1’Q0 2.