基于IP软核的IC设计-微电子学与固体电子学专业论文.docxVIP

IC IC design base on IP SOft core Abstract Development and use of IP cores has been the main design method for SoC (System on a Chip)design since the IC design enters into SoC design era．IP core can be composed of three parts：soft core，hard core， ．they can be divided by different process．Now we can firstly design many IP,then these IP can be made of ASIC．IP is independent．However,IC design in China develops latter than some other countries，it is significant for US to design the IP cores which belong to US． In system architecture，1 will introduce JPEG Decoder IP by soft core．With the development of multimedia tech，more and more people improve their demands for digital imagine．JPEG is a kind standard of image，but it can apply for a lot of field， eg．network，picture，communication and SO on．For sarisfying all requiment about quality of image，we use a new arithmetic to speed decode codes．We chose hardware to finish decoding SO that IP didn’t disturb CPU． In’arithmetic，in Huffman model，the paper introduces a method about the design and implementation of the parallel of huffman decoder in JPEG．This parallel frame can run both stream parser and decode．This method needs more pipelines and occupation of hardware source，but it will provide efficiency of decoding code—word The JPEG Decoder IP core designed in this thesis pass the full functional verification and FPGA hardware verification． Key Words：JPEG，FPGA，stream parser，huffman，IDCT，min-code，IP II 插图清单图1．1 插图清单 图1．1 可重用IP核设计流程 3 图1．2 系统级验证平台生成流程 5 图2．1 编解码流程图 ．7 图3．1 JPE0系统 ．1l 图3．2 FPGA的实现流程 ．12 目日4．1 JPEG decoder IP top ．15 图4．2 各个模块之间的关系 ．．16 图4-3 JPEG decoder IP的时序图 。16 图4-4 stream parser的模块接口 ．25 图4．5 head parser的时序 ．．27 图4．6 ECS parser的时序图 27 图4．7 stream parser流程图 ．．28 图4．8 状态机跳转图 30 图4-9 未确定标识状态下的实现码流分析的流程图 3l 图4．10 ESC parser的流程图 ．．32 图4．1l Mark process 33 图4．12 No．Mark process 34 图4．13 Huffman解码重启控制图 36 图4．14 Huffman解码流程图 37 图4．15最小码的处理 ．38 图4．16并行检测流程图 。38 图4．17解amplitude的流程图 39 图4．18解run／size流程图 40 图4．19结构框图 ．．40