第2章数字ic设浩计方法学.pptVIP

module ALU(op,a,b,s,n,v,c,z); input [1:0] op; input [31:0] a,b; output [31:0] s; output n,v,c,z; wire [31:0] d,e,f,s1; assign d=ab; assign e=a|b; mux21_32 u0(f,d,e,op[0]); add u2(a,b,op[0],s1,c,v,n); mux21_32 u1(s,f,s1,op[1]); assign z=~(|s); endmodule ALU的Verilog模型 ALU的测试文件 `timescale 1ns / 1ns module ALUtest; reg clk; reg [1:0]op; reg [31:0]a,b; wire [31:0]s; wire n,v,c,z; //op=00 AND;op=01 OR;op=10 ADD;op=11 SUB; ALU A(op,a,b,s,n,v,c,z); initial clk = 1; //clock generation always #50 clk = ~clk; initial begin #20 a=32b0100_0101_0100_0000_0010_0010_0101_000