基于8086单芯片计算机外设ip软核设计技术的研究-检测与自动化装置专业论文.docxVIP

The The Research on design methodology of several peripheral soft IPs in 8086一based Single—-Chip PC Abstract ITRS expected that semiconductor technology scale would enter 45·nanometer era in the year of 20 1 0 and more than one billion transistors would be integrated into a Single chip．According to this trend，all circuit modules(except monitor and keyboard)of single PC can be integrated in a chip，which is the single-chip computer．The research in this thesis is based on the project of the minimum set of 8086-based Single—Chip PC．In this paper the author adopted the IP／SoC design methodology and designed two important peripheral IPs-programmable peripheral interface a8255 IP and programmable peripheral interval timer a8254 IP．These two IPs are fully instruction-level compatible with 8255 chip and 8254 chip．Then the integration verification of them into a single—chip computer platform is realized． In order to increase testability and debuggability of the platform，this paper also discussed boundary-scan technique and designed the boundary·scan circuit—JTAG debugging module． The experimental results show that both the two peripheral IPs and JTAG debug module can well meet the design requirements． The main WOrk and achievements are as follows： 1)A kind of 8086 CPU—based single—PC platform architecture is discussed and design of two peripheral IP cores a8255 and a8254 are implemented．Independent functional verification of them and it integration into the minimum set of Single-Chip PC platform is also discussed； 2)Design of JTAG debug module based on IEEE 1 1 49．1 standard is presented to afford test and debug interface for Single-Chip PC． Key words：System—on·a—Chip， Single—Chip PC， Interface IP, Debug module， JTAG III 插图清单图1．1 插图清单 图1．1 HGD8086体系结构 3 图1．2单芯片计算机平台结构 ．．4 图2．1 I／O接口的典型结构 7 图2．2 a8255外特性 ．8 图2．3 a8255内部结构 ．11 图2-4 a8255 RTL级模块结构图 ．11 图2．5 a8255模式0仿真波形 ．1 6 图2-6 a8255模式1仿真波形 ．16 图2．7 a8255模式2双向仿真波形 ．1 7 图2．8 a8254外特性 1 8 图2．9 a8254模式0波形 ．21 图2．10 a8254模式1波形 2