集成电路成品率的版图灵敏度模型-研究.doc

摘要 摘要 在深亚微米技术节点，成品率设计，尤其是版图设计阶段的成品率设计是解 决可制造性问题和成品率问题的重要途径。为了减少由冗余物缺陷所引起的成品 率损失，选择优先进行优化的候选线网成为版图优化过程中的一个重要课题。 本文提出了一种新的短路灵敏度模型，该模型以线网为单位，反映了单位面 积膨胀后的线网上该线网与周围线网间的关键面积的大小。由于本文的灵敏度模 型是关于单一线网的，同时又包含候选线网周围线网的信息，因此，在优化时可 以同时减少候选线网与周围线网之间的短路关键面积，提高了版图优化的效率。 与以往的考虑芯片面积或者考虑基本版图的信息灵敏度模型相比，本文提出的短 路灵敏度模型不仅优化效率高，而且更加适用于版图优化时待优化线网的选择。 关于开路灵敏度模型，因为灵敏度模型的研究最终是为了进行版图优化设计 以提高成品率，所以本文提出了考虑线网优化空间的开路灵敏度模型。该模型综 合分析了线网进行优化的必要性和可能性，可以确保选取的优化位置能够进行高 效的版图优化。 关键词：成品率 可制造型设计 局部缺陷 版图优化 关键面积 版图灵敏度 Abstract Abstract For modern processes at 90-nm and 65-nm technology nodes, yield design, especially the yield design at the stage of layout design is an important way to resolve the problem about manufacturability and yield. In order to reduce the yield loss caused by redundancy material defect, choosing the alternative net which to be optimized at first is become an important problem in the process of layout optimization. The paper provides a new NSS-net Sensitivity for short model, which is net-based and reflects size of the critical area between the single net and the nets around it. Because of this model is based on single net and includes the information of the surrounding net，the critical area between the single net and the nets around it can be reduced at one time. By this way, the efficiency of layout optimization becomes higher. According to the experiment, this sensitivity model can be used to choose the position for optimization. Comparing with the chip area based and basic layout based sensitivity model, this sensitivity model in the paper not only bears higher efficiency, but also hold true for choosing the net which to be optimized at first. On the short circuit sensitivity model, because the sensitivity model is ultimately for layout optimization design in order to improve the yield， so this paper proposes a new short-circuit sensitivity model which considering the optimization space. The model provides a comprehensive analysis of the possibility and necessity about net optimization。