综合软件synplify pro的使用.pptVIP

综合工具synplify 实验目的 熟悉一下Synplify pro综合工具的使用，走一遍综合流程 Synplify、Synplify Pro和Synplify Premier是Synplicity公司提供的专门针对FPGA和CPLD实现的逻辑综合工具,Synplicity的工具涵盖了可编程逻辑器件（FPGAs、PLDs和CPLDs）的综合，验证，调试，物理综合及原型验证等领域。 2008年被Synopsys公司收购 The Synopsys FPGA Product Family Synplify and Synplify Pro Software Synplify? and Synplify Pro? are logic synthesis tools for FPGAs (Field Programmable Gate Arrays) and Complex PLDs (Programmable Logic Devices). For input, the software uses high-level designs written in Verilog and VHDL hardware description languages (HDLs). Using proprietary Behavior Extracting Synthesis Technology? (B.E.S.T.)? the tool converts the HDL into small, high-performance, design netlists that are optimized for popular technology vendors. Optionally, the software can write post-synthesis VHDL and Verilog netlists that you can use to verify functionality through simulation. The Synplify Pro software offers a superset of the Synplify features. Synplify Premier Software The Synplify Premier tool offers a push-button, graph-based physical synthesis approach improving overall device performance while simultaneously delivering tight correlation between pre-route timing estimates and final post place-and-route results. 实验室软件环境 Synplify9.6.1版本 软件破解说明： /viewthread.php?tid=758extra=page%3D1 //以shifter为例，做一下实验(实例可以自选) 逻辑综合设计流程 选择File-New-Project File(Project)新建一个工程 选择Add File…添加设计文件shifter.v文件 可以选择Run-Syntax Check完成语法检查，Synthesis Check完成综合检查 语法上没有错误的话，接下来可以进行综合选项的设置工作 选择Implementation Options…进行综合选项设置 在上图中选择device和一些option选项 接下来选择Run执行 编译(Compiling) 特性分析注释(Annotating Analyst Properties) 映射(Mapping) View Log查看输出结果 选择HDL-Analyst-RTL-Hierarchical View或快捷工具 查看编译结果 选择HDL-Analyst-Technology-Hierarchical View或快捷工具 查看编译结果 RTL View显示的是高层的与目标技术无关的原理图，是对编译结果的可视化显示 Technology View显示的是相对底层的、特定厂商器件实现的原理图，是对映射结果的显示，显示的基本元是与特定器件技术有关的，如查找表、级联、多路器与触发器等 综合完成后，工程目录rev_1下生成.vqm格式的门级网表，用于布局、布线 //因为synplify不具有布局布线的功能，需要启动quartus或其他软件完成布局布线 Constraint File(Scope)，电子表格界面，用于