CMOS乘法器版图设计与仿真——第1章-第4章.doc

精品文档 知识共享 摘 要 先进的数字系统为实现高速算术运算都包含有乘法器电路，通常乘法器处于关键延时路径上，因此乘法器的速度对整个系统性能有重要影响。高速，低功耗,版图规则和占用较少的面积是目前乘法器的设计目标。 通常乘法器速度取决于算法及结构。乘法器按结构可分为串行（阵列）乘法器和并行乘法器，串行乘法器面积和功耗最小，但是运算速度也最慢，因此高速数字应用系统通常会采用并行乘法器。 本文通过对移位相加串行阵列乘法器和并行阵列乘法器工作原理的深入分析，设计出了4X4位的串行乘法器和4X4位并行乘法器，对它们的延时，面积等参数进行了比较，并对所设计电路的版图仿真。经过对比2种乘法器的性能，确定并行乘法器比串行乘法器的性能优越，因此高速数字应用系统通常会采用并行乘法器。 在并行乘法器结构基础上，采用层次化设计方式设计出无符号8X8位并行乘法器；在无符号8X8位并行乘法器基础上，设计了符号位扩展，完成了带符号位8X8位并行乘法器的原理图设计、版图设计和后端仿真，并给出了带有延时参数的仿真波形图。 完通过对8X8位并行乘法器结构的分析研究，对带符号8X8并行乘法器设计进行了优化，并完成了优化后带符号8X8并行乘法器的原理图设计、版图设计和后端仿真，经过对比优化前后带符号8X8并行乘法器的运算速度、面积等参数，并比较版图仿真的延时参数，确定经过优化的乘法器性能比优化前更优秀。 关键词： 数字乘法器；并行乘法器；串行乘法器；加法器阵列 Abstract With the fast development of integrate circuit technology, the use of powerful EDA tools in the digital design is needed while the scale and the complex of design has increased incessant, also the design cycle is shorted. Especially the micron-electronics with deep-inferior micron, the integration degree of the single slice can be reached to millions transistor, the change of technology has a great effect with the chips, even with the success or fail of system design. This paper is mainly about how to use the cadence EDA tools which developed with the company of cadence to design a CMOS Digital Multiplier. In this paper is mainly introduced the main principle of the digital array multiplier and discussed the advantage of each other. Then 4X4 bit serial multiplier and 4X4 bit parallel multiplier have been designed, we discussed the delay and the area of both multiplier. With the stimulate of the layout of both 4X4 bit multipliers, inproved that the 4X4 bit parallel multiplier is much speeder than 4X4 bit serial multiplier, so the parallel multiplier is always used in the high speed digital application system. Put forward the design of 8X8 bit parallel multiplier which based on the administrative levels. Designed the sign bit extension and finished the schematic, layout and stimulation with layout of 8X8 bit parallel multiplier with sign bit