SoCVerification-国立中正大学资工系.PPT

Design Verification for SoC 晶片系統之設計驗證 熊博安國立中正大學資訊工程學系嵌入式系統實驗室 hpa@.tw/~pahsiung/.tw/ Contents SoC Verification Challenges Verification Methods Simulation Technologies Static Technologies Formal Technologies Physical Verification and Analysis SoC Verification Methodologies Case Studies What is a System-on-Chip? An SoC contains: Portable / reusable IP Embedded CPU Embedded Memory Real World Interfaces (USB, PCI, Ethernet) Software (both on-chip and off) Mixed-signal Blocks Programmable HW (FPGAs) 500K gates Technology: 0.25um and below Not an ASIC ! Challenges for System-on-Chip Industry “ ... the industry is just beginning to fathom the scope of the challenges confronting those who integrate blocks of reusable IP on large chips. Most of the participants summed up the toughest challenge in one word: verification.” Source: EE Times (Jan. 20, 1997) Report on Design Reuse and IP Core Workshop Organized by DARPA, EDA Industry Council, NIST System-on-Chip Verification Challenges Verification goals functionality, timing, performance, power, physical Design complexity MPUs, MCUs, DSPs, AMS IPs, ESW, clock/power distribution, test structures, interface, telecom, multimedia System-on-Chip Verification Challenges Diversity of blocks (IPs/Cores) different vendors soft, firm, hard digital, analog, synchronous, asynchronous different modeling and description languages - C, Verilog, VHDL software, firmware, hardware Different phases in system design flow specification validation, algorithmic, architectural, hw/sw, full timing, prototype Finding/fixing bugs costs in the verification process Challenges in DSM technology for SoC Timing Closure Sensitive to interconnect delays Large Capacity Hierarchical design and design reuse Physical Properties Signal integrity (crosstalk, IR drop, power/ground bounce) Design integrity (electron migration, hot electron, wire self-heating) Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity Subs