基于FPGA的频率计设计与实现毕业设计.doc

PAGE 毕 业 设 计 设计题目：基于FPGA的数字频率计设计与实现 PAGE 基于FPGA的数字频率计设计与实现 摘 要 在电子设计领域，随着计算机技术、大规模集成电路技术、EDA(Electronics Design Automation)技术的发展和可编程逻辑器件的广泛应用，传统的自下而上的数字电路设计方法、工具、器件已远远落后于当今技术的发展。基于EDA技术和硬件描述语言的自上而下的设计技术正在承担起越来越多的数字系统设计任务。 本课题的数字频率计设计，采用自上向下的设计方法。本文首先综述了EDA技术的概况，接着介绍硬件描述语言VHDL，可编程器件FPGA及频率测量的一般原理；然后介绍数字频率计的系统设计，频率计各系统模块的VHDL语言实现，最后利用QUARTUS Ⅱ集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，此频率计具有较高的实用性和可靠性。 关键字：EDA FPGA 数字频率计 VHDL语言 \o 添加到单词本 \o 添加到单词本 Design and Implementation of Digital Frequency Meter Based on FPGA Abstract In the field of electronic design, with the development of computer technology, LSI technology, EDA (Electronics Design Automation)technology and wide application of programmable logic devices, the traditional bottom-up digital circuit design methods, tools, devices have far behind todays technology. The top-down design techniques based on EDA technology and hardware description language are taking on more and more digital system design task. The topic digital frequency meter design uses top-down design approach. First, this paper summarizes the overview of EDA technology, then it describes the hardware description language which is called VHDL, FPGA programmable device and the general principles of frequency measurement; then it introduces the system design of digital frequency meter, and the realization of frequency meter each system module VHDL. Finally using QUARTUSⅡ integrated development environment edits, synthesizes, and simulates, and download to the CPLD devices, by using the actual circuit testing, simulation and experimental results show that this frequency meter is high availability and reliability. Keywords: EDA; FPGA; digital frequency meter; VHDL language 目 录 TOC \o 1-3 \h \z \u 1 引言 1 2 硬件描述语言（HDL） 2 2.1VHDL语言简介 2 2 .2 利用VHDL语言开发的优缺点 3 3 电子设计自动化（EDA）发展概述 4 3.1 EDA的简介 4 3.2 EDA的发展史 4 3.3基于EDA的FPGA/CPL