基于FPGA的8位硬件乘法器设计_毕业设计.docVIP

PAGE 基于FPGA的8位硬件乘法器设计 本科毕业设计 基于FPGA的8位硬件乘法器设计 摘 要 VHDL（VHSIC Hardware Description Language）是当今最流行的硬件描述语言之一，能够对最复杂的芯片和最完整的电子系统进行描述。以硬件描述语言作为设计输入，经过简单的综合与布局，快速烧录至FPGA（Field Programmable Gate Array）上进行测试，是现代IC设计验证的技术主流。 乘法器是处理器进行科学计算和数字信号处理的基本硬件结构，是现代微处理器中的重要部件。乘法器完成一次乘法操作的周期基本上决定了微处理器的主频。本文基于FPGA，采用VHDL语言，结合MAX+plusⅡ这个强大的软件平台设计了8位二进制乘法器，并对其进行符号扩展，使其可以统一处理8位带符号数和无符号数。 高速乘法器设计通常分为三个关键步骤：部分积产生、部分积累加和最终结果获得。本文对部分积产生过程采用改进Booth算法，有效减少部分积加法项；为了统一带符号和无符号数，对部分积进行符号扩展；而对部分积的累加则采取3-2压缩器和4-2压缩器进行压缩；最终结果的获得则以一个根据部分积累加结果到达时间的不同进行延迟优化的选择进位加法器将累加结果和累加进位相加而得。 关键词：乘法器 改进Booth算法 压缩器 选择进位加法器 The Circuit Design of 8-bit Hardware Multiplier Based on FPGA Ke Xiuyan (College of Engineering, South China Agricultural University, Guangzhou 510642, China) Abstract: VHSIC Hardware Description Language, one of todays most popular hardware description languages, is used to describe the most complex chip and most complete electronic systems. The multiplier is not only the basic hardware structure of the processor for scientific computing and digital signal processing but also an important component of modern microprocessors. This design for 8-bit binary multiplier is based on FPGA, using VHDL language, and proved by the MAX+plusⅡ software platform. The multiplicand has an extended sign bit so that the multiplier can unify 8-bit signed and unsigned. High-speed multiplier design is usually divided into three key steps: partial product generation circuit, accumulator and adder. In this paper, the partial product generation process uses the modified Booth algorithm, so that the partial product addition terms can be effectively reduced. The accumulation of partial products takes 3-2 compressor and 4-2 compressor to compress. The final result is obtained with select carry adder. Key words: multiplier the modified Booth algorithm compressor select carry adder 目 录 TOC \o 1-3 \h \z \u 1 前言 h 1 1.1 乘法器的研究背景和意义 h 1 1.2 乘法器的研究发展状况 h 1 2 总体方案确定 h 2 2.1 乘法器