Verilog- H- D- L- Overview培训课件.pptVIP

Example module MUX4x1 (Z, D0, D1, D2, D3, S0, S1); output Z; input D0, D1, D2, D3, S0, S1; and (T0, D0, S0BAR, S1BAR); (T1, D1, S0BAR, S1), (T2, D2, S0, S1BAR), (T3, D3, S0, S1); not (S0BAR, S0), (S1BAR, S1); nor (Z, T0, T1, T2, T3); endmodule 4 X 1 multiplexer circuit OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Simulation and test bench Data-flow modeling(1) Models behavior of combinational logic Assign a value to a net using continuous assignment Examples: wire [3:0] Z, PRESET, CLEAR; assign Z = PRESET CLEAR; wire COUT, CIN; wire [3:0] SUM, A, B; assign {COUT, SUM} = A + B + CIN; Data-flow modeling(2) Left-hand side (target) expression can be: Single net (ex: Z) Part-select (ex: SUM[2:0]) Bit-select (ex: Z[1]) Concatenation of both (ex: {COUT, SUM[3:0]}) Expression on right-hand side is evaluated whenever any operand value changes Note: Concatenation example {A,1’b0} - x2 {A,2’b0} - x4 wire [7:0]A,B; wire [16:0]C; assign C={A,B}; Delay Delay between assignment of right-hand side to left-hand side assign #6 ASK = QUIET || LATE; //Continuous delay Netdelay wire #5 ARB; // Any change to ARB is delayed 5 time units before it takes effect If value changes before it has a chance to propagate, latest value change will be applied – Inertial delay OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Simulation and test bench Behavioral modeling Procedural blocks: initial block: executes only once always block:executes in a loop Block execution is triggered based on user-specified conditions always @ (posedge clk) ……… All procedural blocks are automatically activated at time 0 All procedural blocks are executed concurrently reg is the main data type that is manipulated within a sequential block It holds its value until