三维片上网络低功耗映射算法分析.pdfVIP

ABSTRACT With the sizeofthe communicationmechanismbetweenthe growing chip，the elementson the is a factorin the processing chipbecomingkey decidingperformance ofa busand interconnectstructureson chip．The the have original point-to-point chip beenunabletomeetthe communicationneedsof thetwo． processingelements，thus dimensional Network—on·Chip(2DNoC)has appeared．However,thepower andotherelementsinthe2DNoC consumption，layout havereachedabottleneck，SO the three-dimensional into the Network—on-Chip(3DNoC)came being．Asintegrated circuit ofthe3DNoCis density needsto gettinghigher,poweroptimizationproblem beaddressed determinesthelocationsof urgently．Mapping intellectual property(IP) coresin3D a Can NoC，and reduce goodmappingalgorithmeffectively power to a onthe3DNoCwiththeminimum consumption．Therefore，howdesign mapping hasbecomeahotresearch power area．Sincethe isthe consumption