【VHDL 程序举例大全-存储器举例：(注3)】.pdfVIP

VHDL - ( 3) 【VVHHDDLL 程序举例大全--存储器举例：((注33))】 --A First-in First-outMemory --afirst-in firstoutmemory,usesasynchronising clock --genericsallowfifosofdifferentsizestobeinstantiated libraryIEEE; useIEEE.Std_logic_1164.all; entityFIFOMXNis generic(m, n:Positive :=8);--misfifodepth,nisfifowidth port(RESET,WRREQ,RDREQ,CLOCK:inStd_logic; DATAIN :inStd_logic_vector((n-1)downto0); DATAOUT:outStd_logic_vector((n-1)downto0); FULL, EMPTY:inoutStd_logic); endFIFOMXN; architectureV2ofFIFOMXNis typeFifo_arrayisarray(0to(m-1)) ofBit_vector((n-1)downto0); signalFifo_memory:Fifo_array; signalWraddr,Rdaddr,Offset:Naturalrange0to(m-1); signalRdpulse,Wrpulse,Q1,Q2,Q3,Q4:Std_logic; signalDatabuffer:Bit_vector((n-1)downto0); begin --pulsesynchronisersforWRREQandRDREQ --modifiedforSynplify toaprocess sync_ffs:process begin waituntilrising_edge(CLOCK); Q1=WRREQ; Q2=Q1; Q3=RDREQ; Q4=Q3; endprocess; --concurrentlogictogeneratepulses Wrpulse=Q2andnot(Q1); Rdpulse=Q4andnot(Q3); Fifo_read:process begin waituntilrising_edge(CLOCK); ifRESET=1 then Rdaddr=0; Databuffer=(others=0); elsif(Rdpulse=1andEMPTY=0) then Databuffer=Fifo_memory(Rdaddr); Rdaddr=(Rdaddr+1)modm; endif; endprocess; Fifo_write:process begin waituntilrising_edge(CLOCK); ifRESET=1 then Wraddr=0; elsif(Wrpulse=1 andFULL=0)then Fifo_memory(Wraddr)=To_Bitvector(DATAIN); Wraddr=(Wraddr+1)mod m; endif; endprocess; Offset=(Wraddr-Rdaddr)when(WraddrRdaddr) else(m-(Rdaddr-Wraddr))when(RdaddrWraddr) else0; EMPTY=1 when(Offset=0)else0; FULL=1 when(Offset=(m-1))