- 3
- 0
- 约2.27万字
- 约 69页
- 2019-07-26 发布于贵州
- 举报
Differential Signaling Introduction Reading Chapter 6 Agenda Differential Signaling Definition Voltage Parameters Common mode parameters Differential mode parameters Current mode logic (CML) buffer Relate to parameters Modeling simulation Timing parameters Clock recovery Embedded clock AC coupling Common mode response Issues with simulation 8B10B encoding DC balanced codes Duty Cycle distortion Cycle Single Ended Signaling All electrical signal circuits require a loop or return path. Single ended signal subject several means of distortions and noise. Ground or reference may move due to swi
原创力文档

文档评论(0)