VHDL入门教程教学课件.ppt

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shift1 IS PORT ( d: IN STD_LOGIC_VECTOR ( 7 DOWNTO 0); clr, clk, load, dir, sr, sl: IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END shift1; ARCHITECTURE arc OF shift1 IS SINGAL a: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN q= a; PROCESS (clr,clk) BEGIN IF (clr=‘0’) THEN a=; ELSEIF (clk’EVENT) AND (clk=‘1’) THEN IF (load=‘0’) THEN a=d; EL