锁相环外文翻译.doc

Phase-locked loop Structure and function Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure. Both analog and digital PLL circuits include four basic elements: Phase detector, Low-pass filter, Variable-frequency oscillator, and feedback path (which may include a frequency divider). Variations There are several variations of PLLs. Some terms that are used are analog phase-locked loop (APLL) also referred to as a linear phase-locked loop (LPLL), digital phase-locked loop (DPLL), all digital phase-locked loop (ADPLL), and software phase-locked loop (SPLL). Analog or Linear PLL (LPLL) Phase detector is an analog multiplier. Loop filter is active or passive. Uses a Voltage-controlled oscillator(VCO). Digital PLL (DPLL) An analog PLL with a digital phase detector (such as XOR, edge-trigger JK, phase frequency detector). May have digital divider in the loop. All digital PLL (ADPLL) Phase detector, filter and oscillator are digital. Uses a numerically controlled oscillator (NCO). Software PLL (SPLL) Functional blocks are implemented by software rather than specialized hardware. Performance parameters Type and order Lock range: The frequency range the PLL is able to stay locked. Mainly defined by the VCO range. Capture range: The frequency range the PLL is able to lock-in, starting from unlocked condition. This range is usually smaller than the lock range and will depend e.g. on phase detector. Loop bandwidth: Defining the speed of the control loop. Transient response: Like overshoot and settling time to a certain accuracy (like 50ppm). Steady-state errors: Like remaining phase or timing error Output spectrum purity: Like sidebands generated from a certain VCO tuning voltage ripple. Phase-noise: Defined by noise energy in a certain frequency band (like 10kHz offset from carrier). Highly dependent on VCO phase-noise, PLL bandwidth, etc. General parameters: Such as power consumption, supply vo