大学毕业论文专业文献翻译案例(高性能低功耗的CMOS动态逻辑运算电路).docVIP

High performance low power CMOS dynamic logic for arithmetic circuits Abstract This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates . Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies. Keywords: Dynamic logic; CMOS digital integrated circuits; CMOS logic circuits; Low power arithmetic circuits; High speed arithmetic circuits Article Outline 1. Introduction 2. Principle of operation 3. Performance results 3.1. Proposed circuit structures 3.2. Comparison of the proposed structure vs. the dynamic domino CMOS 4. Conclusion Acknowledgements References 1. Introduction Domino CMOS is widely used in high performance integrated circuits. It reduces the device count and silicon area, and improves performance when compared to the standard fully complementary static CMOS logic [1] and [2]. However, the major drawback with the domino dynamic logic circuit is its excessive power dissipation due to the switching activity