lect21-封装 电源与时钟教学课件.ppt

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 21: Package, Power, and Clock CMOS VLSI Design CMOS VLSI Design 4th Ed. Lecture 21: Packaging, Power, Clock 21: Package, Power, and Clock * Outline Packaging Power Distribution Clock Distribution 21: Package, Power, and Clock * Packages Package functions Electrical connection of signals and power from chip to board Little delay or distortion Mechanical connection of chip to board Removes heat produced on chip Protects chip from mechanical damage Compatible with thermal expansion Inexpensive to manufacture and test 21: Package, Power, and Clock * Package Types Through-hole vs. surface mount 21: Package, Power, and Clock * Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame Metal pads on 100 – 200 mm pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling 21: Package, Power, and Clock * Advanced Packages Bond wires contribute parasitic inductance Fancy packages have many signal, power layers Like tiny printed circuit boards Flip-chip places connections across surface of die rather than around periphery Top level metal pads covered with solder balls Chip flips upside down Carefully aligned to package (done blind!) Heated to melt balls Also called C4 (Controlled Collapse Chip Connection) 21: Package, Power, and Clock * Package Parasitics Use many VDD, GND in parallel Inductance, IDD 21: Package, Power, and Clock * Heat Dissipation 60 W light bulb has surface area of 120 cm2 Itanium 2 die dissipates 130 W over 4 cm2 Chips have enormous power densities Cooling is a serious challenge Package spreads heat to larger surface area Heat sinks may increase surface area further Fans increase airflow rate over surface area Liquid cooling used in extreme cases ($$$) 21: Package, Power, and Clock * Thermal Resistance DT = qjaP DT: temperature rise on chip qja: thermal resistance of chip junction to ambient P: power dissipation o