02集成电路工艺和版图设计参 考.pptVIP

Jian Fang Jian Fang 集成电路工艺和版图设计概述Jian FangIC Design Center, UESTC 微电子制造工艺 版图设计（layout）及相关技术 Cell development (Analog/digital)Analog design Schematic entry (transistor symbols) Analog simulation (SPICE models) Layout (layer definitions) Design Rule Checking, DRC ( design rules) Extraction (extraction rules and parameters) Electrical Rule Checking, ERC (ERC rules) Layout Versus Schematic, LVS ( LVS rules) Layout Drawing geometrical shapes: Defines layout hierarchy Defines layer masks Requires detailed knowledge about CMOS technology Requires detailed knowledge about design rules