数字逻辑3-3n-公开课件（设计）.pptVIP

* * Structure : complement switchs steady state : voltage and current Dynamic state : Speed and cost Chapter 3 Digital circuit Cg: gate capacitor Cd and Cs: junction capacitors Dynamic model of CMOS Any device has input and output capacitors ! Dynamic model of CMOS Dynamic behavior When state changed, capacitors must be charged or uncharged through a resistor ! Analyze without resistive load High state : VH=5V Low state : VL=0V From H to L : From L to H : Dynamic behavior From H to L : fall time From L to H : rise time High state : VH=? Low state : VL=? From H to L : From L to H : Analyze with resistive load DC Driven ability 1/Ron Limitation for output current and resistive load. Time constant Ron Time delay and frequency limit. The importance for Ron If Ron in all the transistors are same ? Ron will be different for devises and states. The optimize design way Make Ron in any devices the same value by adjust transistor width. Ron 1/W; C W; A W. When Routput in any devices should be same: DC driven ability for any devices are same; Rise time and fall time of one devices are same ; Delay time of a device will be only rely on its capacitors. The optimize design way Fan-in :The input numbers of a single device If we use smaller device for design , we can get better result ! For VLSI design of CMOS devices: Use parallel design to limit the fan-in The fan-in should be less than 6 ! Use parallel design for positive output Output driven and load on line When output is connected with more than one input, the time delay will be longer ! Time delay on the connected line Time delay on the connected line Dynamic power consumption Power consumption is mainly happened when the state is changed! Diode logic Other digital circuit  Simple , fast , but the driving ability is weak ! Transistor-Transistor Logic : TTL circuit Diode logic---Inverter---Output driver Other digital circu