时序电路设计计数器.pptVIP

8.5.2 MSI Shift Registers(MSI移位寄存器) CLK CLR SERA SERB 74x164 QA QB QC QD QE QF QG QH CLK CLKINH SH/LD CLR SER A B C D E F G H QH 74x166 SERA·SERB an MSI 4-bit bidirectional, parallel-in, parallel-out shift register  (4位双向移位寄存器74x194) CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN 74x194 left-in 左移输入 right-in 右移输入 left means “in the direction from QD to QA,” right means “in the direction from QA to QD.” Function table for the74x194 4-bit universalshift register 00 S1S0 保持 S1’ S0’ S1 S0 10 左移 01 右移 11 载入 Qi* = S1’·S0’·Qi + S1’·S0·Qi-1 + S1·S0’·Qi+1 + S1·S0·INi The 74x194 4-bit universalshift register CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN 74x194 CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN CLK CLR S1 S0 LIN RIN 移 位 寄 存 器 的 扩 展 并行输入 （8位） 并行 输出 8位 8.5.3 Shift-Register Counters Serial/parallel conversion is a “data” application, but shift registers have “nondata” applications as well. A shift register can be combined with combinational logic to form a state machine whose state diagram is cyclic. Such a circuit is called a shift-register counter. Unlike a binary counter, a shift-register counter does not count in an ascending or descending binary sequence, but it is useful in many “control” applications. 8.5.5 Shift-Register Counters(移位寄存器计数器) D0 = F ( Q0 , Q1 , … , Qn-1 ) 反 馈 逻 辑 D Q CK Q D Q CK Q D Q CK Q D Q CK Q CLK FF0 FF1 FF2 FF3 一般结构： 1000 0100 0001 0010 有效状态 其他状态 8.5.6 Ring Counters (环型计数器) D Q CK Q D Q CK Q D Q CK Q D Q CK Q CLK FF0 FF1 FF2 FF3 1000 0100 0001 0010 D0 D1 D2 D3 —— 非自启动的 无效状态 D0 = Qn-1 self-correcting counter self-correcting counter is designed so that all abnormal states have transitions leading to normal states. Self-correcting counters are desirable for the same reason that we use a minimal-r