基本数字电路EDA实现.pptVIP

进制计数器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY count128 IS PORT(f10MHz :IN STD_LOGIC; clr,en,load:IN STD_LOGIC; din :IN STD_LOGIC_VECTOR(7 DOWNTO 0); q :BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)); END count128; ARCHITECTURE a OF count128 IS SIGNAL cnt:INTEGER RANGE 0 TO SIGNAL clk:STD_LOGIC; BEGIN PROCESS(f10MHz) BEGIN IF f10MHzEVENT AND f10MHz=1 THEN IF cnt=4999999 THEN cnt=0;clk=NOT clk; ELSE cnt=cnt+1; END IF; END IF; END PROCESS; PROCESS(clk) BEGIN IF clke