数字设计基础双语课件（第8章）.pptVIP

* * * * * * * * * 8. Motivation for HDL 8.1 Problems with low level methods 8.2 Hardware Description Languages 8.3 Behavioral and structural description 8.4 Synthesis and Simulation * 8.1 Problems with low level methods Low level methods of logic design require the designer to get heavily involved in what each logic gate and flip-flop must do. 1. low level methods 2. higher level methods Higher level methods aim to free the designer from the detail by automating the low level tasks and to enable them to concentrate on the overall architecture of a digital system. * 8.2 Hardware Description Languages 1. Two important HDLs: VHDL and Verilog Exp1: Describe a comparator in two HDLs. VHDL: g = ’1’ when ab else ’0’; Verilog: assign g = ab ? 1 : 0; VHDL is the VHSIC Hardware Description Language. VHSIC stands for Very High Speed Integrated Circuit. * 8.2 Hardware Description Languages To provide a language for rigorous and unambiguous specification of modules. Gradually it developed to be used for other purposes such as synthesis. 2. Main motivation for VHDL * 8.3 Behavioral and structural description Behavioral descriptions tell us what the design should do but not how we would make it. 1. Two kinds of descriptions in VHDL （1）Behavioral descriptions （2）Structural descriptions 2. Behavioral descriptions * 8.3 Behavioral and structural description Exp2: It has two inputs, a and b, both of which represent four-bit binary numbers. There is a single one-bit output g, which represents the “greater than” condition. When ab then g=1; otherwise g=0. Behavioral description in VHDL: g = ‘1’ when ab else ‘0’; The behavioral description doesnt give us any clues as to how we would build a circuit that accomplished the function. * 8.3 Behavioral and structural description Structural descriptions tell us how we would make it but not what it would do. 3. Structural descriptions It tells us how we would connect together several simpler u