数字的设计 数字电路第六章.ppt

Chapter6  Combinational Logic Design Practices;Chapter Outline;6.1 Documentation Standard(文档标准) ;Block Diagram;Schematic Diagram;Hierarchichal schematic structure;Documentation Standard(文档标准);Gate Symbols (门的符号);DeMorgan equivalent symbols(等效门符号（摩根定理）);Signal Names and Active Levels (信号名和有效电平);READY;Signal Name and Active Levels (信号名和有效电平);Bubble-to-Bubble Logic Design(“圈到圈”的逻辑设计);Bubble-to-Bubble Logic Design(“圈到圈”的逻辑设计);6.2 Circuit Timing (电路定时);Propagation Delay;Timing Diagram 定时图（时序图）;GO;6.2 Circuit Timing (电路定时);Commonly Used MSI Combinational Logic Device;Decoder and Encoder(译码器和编码器);Decoder（译码器） Normally Output Code has More bits than its Input Code (一般来说，输出编码比输入编码位数多) Encoder（编码器） Output Code has Fewer bits than its Input Code called an Encoder (输出编码比输入编码位数少，则常称为编码器);Most Commonly Used Case;6.4 Decoder（译码器）;Y0 = EN · ( I1’ · I2’ ) Y1 = EN · ( I1’ · I2 ) Y2 = EN · ( I1 · I2’ ) Y3 = EN · ( I1 · I2 );The 74x139 Dual 2-to-4 Decoder(双2-4译码器74x139); Logic Symbols for Large-Scale Element;0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0;The 74x138 3-to-8 Decoder(3-8译码器74x138);Enable;用74x138设计4-16译码器;Consider: How to make a 5-to-32 Decoder with 3-to-8 Decoder? 32个输出需要多少片74x138？ 控制任何时刻只有一片工作 —— 利用使能端 5个输入的低3位控制输入 5个输入的高2位控制片选 —— 利用 2-4 译码器;Use decoder and Gates to realize logic function;Use decoder and Gates to realize logic function;Use decoder and Gates to realize logic function;= M1 · M2 · M4 · M5;BCD Decoder (二－十进制译码器);二-十进制译码器;Seven-Segment Decoders(七段显示译码器);LED;Input code: 4-bit BCD 输入信号：BCD码（用A3A2A1A0表示） Output Code: Seven-Segment Code 输出：七段码（的驱动信号）a ~ g 1 --- On，0 --- Off;74LS48显示字型与输入的对应关系;;;Yc = A3A2 + A2A1A0;Karnaugh Maps for BCD-Seven-Segment Decoder (BCD - 七段显示译码器的卡诺图);Karnaugh Maps for BCD-Seven-Segment Decoder (BCD - 七段显示译码器的卡诺图);D