北邮数字逻辑课程设计.pptVIP

;;实验要求;;模16计数器;ispLSI 1032; LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY example1 IS PORT ( x1, x2, x3 : IN BIT ; f : OUT BIT ) ; END example1 ; ARCHITECTURE LogicFunc OF example1 IS BEGIN f = (x1 AND x2) OR (NOT x2 AND x3) ; END LogicFunc ; ;;实体说明、结构体格式;实体说明、结构体格式; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY counter IS PORT (clk, areset, sset ,enable : IN std_logic; cout : OUT std_logic; q : BUF