HV-Process-and-Device高压工艺与器件教学文案.pptVIP

TD-HV Agenda High voltage product application HV Technology introduction HV voltage standard device 0.5um 5V/40V Mixed-signal Technology Features 0.5um 5V/40V Mixed-signal Design Flexibility 0.5um HV Mixed-Signal Process FlowModules Issue in development High voltage product application NO. Operation Voltage Main Application 1 600V~700V HV Switch, PFC, Power Converter, AC motor control 2 40V~200V Driver (cover PDP driver), Power Converter, Motor Driver 3 ≤40V Power Converter, Power Protection, LDO, Power Charger, Motor Driver, Buffer (Data Driver), Regulator, display driver, ink-jet printer HV Technology introduction E=V/d E1E2E3 P+ N+ d1 V E1 P+ N- d2 V E2 d3 P- N- V E3 PN junction: HV Technology introduction Junction Termination Technology Field plate (MFP-Metal field plate and RFP-resistive field plate) Field limiting Ring-FLR RESURF (Reduced SURface Field) Drain HNW N+ N+ Psub Source Gate FOX HPW N-/P- High voltage Standard Device DDD Structure HVMOS(for 8~12v) N+ N+ N+ NDD POLY FOX P-sub Drain Source N+ OD CO FOX NDD Note: NDD formation through N plus twice implant , only for big dimension process High voltage Standard Device NDD N+ N+ N+ NDD POLY FOX FOX P-sub Drain Source N+ OD CO 16V DDD + Offset HVMOS (for 12~20v) Note: With additional layer NDD after poly High voltage Standard Device LDMOS High Current output; Low dissipation output CDMOS technology is created by merging LDMOS technology and CMOS technology. The majority of CDMOS processes are used for driver and power ICs. Adding BJT options, CDMOS will become BCD process. CMOS High density digital and analog CDMOS High density digital and analog; High Current output; Low dissipation output High voltage Standard Device HNW N+ N+ Psub Source POLY FOX HPW HNW N+ OD CO 40V Metal Above 30v (LDMOS-lateral double diffusion MOS) 40/25V (Vds/Vgs) device structure Critical dimension: A: Channel length A affect the breakdown of punch through and Rdson B: