hct多线切割机介绍(英文原版).docVIP

Applied HCT Wafering Systems POWERING THE c -Si ROADMAP THE CHALLENGE Driving c-Si to below $1 per watt The rapid expansion of solar energy is fueled by a relentless reduction in cost per watt. Because silicon and wafering represent over 50% of total module cost, advances in wafering technology are paramount. Applied HCT, the world leader in wafering technology, is accelerating the c-Si roadmap with process solutions to attack all high leverage areas that reduce wafer cost. From advances in platform architecture that enhance productivity and performance, to accelerating new wire technology, Applied HCT is propelling the industry forward with unique wire saw innovation. Silicon and wafering are 50% of module cost $1.40 $1.20 $1.00 $0.80 Modules Cells Modules Silicon and wafering costs together represent over 50% of module cost. They must be reduced dramatically to meet industry cost reduction objectives. $0.60 Cells $0.40 $0.20 Poly and Wafer Poly and Wafer $0 Current Target Wafering influences nearly 2/3 of wafer costs Wafer Cost Slicing Yield Capital Costs Wafer Si Consumables Material Yield (kerf) Wafering Wire size has a major impact on silicon cost through kerf loss. Process optimization drives nearly 1/4 of total wafer cost, primarily through slicing yield, wire and slurry consumables and tool ?xed costs. Process performance has direct impact on wafer slicing yield. Wafering process optimization is also critical to achieve even thinner wafers. Wafering cost reduction strategies Thinner Wire Higher Table Speed Lower Wire Speed Increased Material Yield Decreased Fixed and Wire Costs Decreased Wire Cost Reduced Productivity and Slicing Yield Reduced Slicing Yield Reduced Slicing Yield Achieving lowest overall wafering cost requires process optimization among multiple variables. Each reduction strategy has potential trade-o?s. An integrated approach to process optimization using platform design ?exibility, advanced consumables and process know-how is requir