常用基本模块VERILOG描述.pptVIP

Table 7.1 Verilog Operators. Verilog Operator Operation Multiplealiort uscc to comp nc bits agical negation logicalAND Bitwise~OR Bitwise Negate user to specify th arithmic D(1) module gatenetwork (A, B, C, D, X,Y); nput A; input B input C input [2: 1]D output X,Y; reg Yi concurrent assignment statemen wire X=A -(BC)(D[1]A D[2D / A/ways concurrent statement- sequential execution inside always @(A or B or C or D) Y=A~(BC)D[^D[2]) endmodule segment d, segment e, segment f, segment g tput segment_ a. segment b, segment c, segment d: @444bbb Case statement implements a logic truth table using gates nent data=7b 111111 c11 411m101 /Multiplexer example shows three ways to model a 2 to 1 mux 7 module multiplexer(A, B, mux_control, mux_out1, mux_out2, mux_out3); Input Signals and Mux Control utput mux out1, mux out2, mux out3 wire mux out1 =(mux control)? B: nent inside a/ways statement always (A or B or mux_control) mux o Case statement inside a/ways statement 7 always ((A or B or mux_control) case(mux contro default: mux out3=A;