第四代PCIe的设备架构.pdfVIP

Device Architectures to Best Enable PCIe Gen 4 Rob Sykes Senior Distinguished Engineer Toshiba America Electronic Components, Inc. Flash Memory Summit 2017 Santa Clara, CA 1 Performance ! Flash Memory Summit 2017 Santa Clara, CA 2 Bottlenecks exist Flash Memory Summit 2017 Santa Clara, CA 3 Introduction • A review of the performance relationship between PCIe Gen 4, NAND (number of planes, channels), controller capabilities and bus architecture and how this relates to top end performance for your systems • Specifically, the presentation will consider the bottlenecks in the system that relate to achieving the front end performance • Bottlenecks exist in the host, the controller architecture in terms of processing power, flash controller, DRAM etc. and the NAND capabilities. • Power, Performance, Price! Flash Memory Summit 2017 Santa Clara, CA 4 System Level Overview Host NVMe / Flash Controller NAND CPU CPU NAND NAND Buffer NAND NAND NVMe