集成电路制造工艺台阶覆盖问题.pdfVIP

集成 电路制造工艺 —台阶覆盖 问题 （西安电子科技大学微电子学院， 西安 710071） 摘要 ： 在特征尺寸减小的情况下,最具挑战性的 问题之一就是如何在小 通孔和互连线中实现保形的阶梯覆盖.随着科学技术的发展，以及社 会的需求，传统的淀积工艺面临巨大的挑战，如何适 社会的需求，克 服工艺中有关台阶覆盖性 问题的困难，寻找更加有效的方法迫在眉睫。 早期的物理气相淀积（PVD）主要制备金属薄膜，且台阶覆盖性差。化 学汽相淀积（CVD）过去一直是薄膜半导体器件淀积的主力。对于不同 的晶粒尺寸,我们都可以实现良好的淀积产出率和相 的阶梯覆盖，该 技术采用挥发性前驱物，受热分解淀积在衬底上形成高质量薄膜。但 用在当前及下一代模块所需的极具挑战性的器件结构时，这种常规工 艺的局限性就很明显。原子层淀积（ALD）是超越 CVD 的技术，迅速被 认可是需要精确控制厚度、台阶覆盖和保形性时应选用的新技术。 关键词 ：半导体 工艺 CVD PVD ALD 台阶覆盖 方法 Abstract: In the characteristic dimensions of decreased, the challenging one of the problems is how little through holes in the interconnect and realize the shape step coverage. With the development of science and technology, 1 and the needs of the community, the traditional deposition process is facing a great challenge, how to adapt to the needs of the community, to overcome the steps in the process of coverage the difficulty of the problem, find a more effective method is imminent. The early physical vapour deposition (PVD) main preparation metal film and steps and poor coverage. Chemical vapor deposition (CVD) used to be thin film deposition of main semiconductor devices. For different grain size, we can achieve good deposition output and the corresponding step coverage, this technology USES volatile precursors, thermal decomposition deposition in the substrate form high quality film. But with the current and the next generation module in the challenging device structure, the limitations of conventional technology was evident. Atomic layer deposition (ALD) is beyond CVD technology, rapid recognition is need precision control thickness, steps and the form sex covered when the new technology should be chosen Keywords: semiconductor;process; CVD PVD;ALD; step coverage;means 1.引言 台阶覆盖性是半导体工艺