C28xm10资料参考 学习.pptVIP

DSP24 12 System Design Module 10 TMS320C28x? MCU Workshop Learning Objectives Emulation and Analysis Block External Interface (XINTF) Flash Configuration and Memory Performance Flash Programming Code Security Module (CSM) Learning Objectives Emulation and Analysis Block External Interface (XINTF) Flash Configuration and Memory Performance Flash Programming Code Security Module (CSM) JTAG Emulation System(based on IEEE 1149.1 Boundary Scan Standard) Emulator Connections to the Device On-Chip Emulation Analysis Block: Capabilities On-Chip Emulation Analysis Block: Hardware Breakpoints On-Chip Emulation Analysis Block: Watchpoints On-Chip Emulation Analysis Block: Online Stack Overflow Detection Emulation analysis registers are accessible to code as well! Configure a watchpoint to monitor for writes near the end of the stack Watchpoint triggers maskable RTOSINT interrupt Works with DSP/BIOS and non-DSP/BIOS See TI application report SPRA820 for implementation details Learning Objectives Emulation and Analysis Block External Interface (XINTF) Flash Configuration and Memory Performance Flash Programming Code Security Module (CSM) TMS320F28335 XINTF Memory Map TMS320F28335 XINTF Signals XINTF Timings Three external zones: 0, 6, 7 Each zone has separate read and write timings XREADY signal can be used to extend ACTIVE phase XINTF Clocking Specify read timing and write timing separately, for each zone: XINTF Registers XTIMINGx specifies read and write timings (lead, active, trail), interface size (16 or 32 bit), X2TIMING, XREADY usage XINTCNF2 selects SYSCLKOUT/1 or SYSCLKOUT/2 as fundamental clock speed XTIMCLK (for lead, active, trail), XHOLD control, write buffer control XBANK specifies the number of XTIMCLK cycles to add between two specified zone (bank switching) XRESET used to do a hard reset in case where CPU detects a stuck XREADY during a DMA transfer XINTF Configuration Example Learning Objectives Emulation and