海大EDA实验1参考答案.pdfVIP

Laboratory Exercise 1 Switches, Lights, and Multiplexers ED 实验参与答案 Part1 library ieee; use ieee.std_logic_1164.all; entity part1 is port(SW :in std_logic_vector(17 downto 0); LEDR :out std_logic_vector(17 downto 0)); end part1; architecture Behavior of part1 is begin LEDR = SW; end Behavior; part2 library ieee; use ieee.std_logic_1164.all; --a 2 to 1 multiplexer entity entity mux21 is port(in_x, in_y, in_s :in std_logic; out_m :out std_logic); end mux21; --a 2 to 1 multiplexer architecture architecture structural of mux21 is signal u, v : std_logic; begin u = in_x and (not in_s); v = in_y and in_s ; out_m = u or v ; end structural; --a eight-bit wide 2 to 1 multiplexer library ieee; use ieee.std_logic_1164.all; --eight-bit wide 2 to 1 multiplexer entity entity mux21_8bit is port( SW : in std_logic_vector (17 downto 0); --SW: in std_logic_vector (15 downto 8); --SW: in std_logic_vector (17 downto 17); LEDR : out std_logic_vector (7 downto 0)); end mux21_8bit; --eight-bit wide 2 to 1 multiplexera rchitecture architecture Structural of mux21_8bit is component mux21 port(in_x, in_y, in_s :in std_logic; out_m :out std_logic); end component; begin U1: mux21 port map (in_x=SW(0), in_y=SW(8), in_s=SW(17), out_m=LEDR(0)); U2: mux21 port map (in_x=SW(1), in_y=SW(9), in_s=SW(17), out_m=LEDR(1)); U3: mux21 port map (in_x=SW(2), in_y=SW(10), in_s=SW(17), out_m=LEDR(2)); U4: mux21 port map (in_x=SW(3), in_y=SW(11), in_s=SW(17), out_m=LEDR(3));