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The Configuration of the CAN Bit Timing
6th International CAN Conference
2nd to 4th November, Turin (Italy)
Florian Hartwich, Armin Bassemir
Robert Bosch GmbH, Abt. K8/EIS
Tübinger Straße 123, 72762 Reutlingen
Abstract:
Even if minor errors in the configuration of the CAN bit timing do not result in
immediate failure, the performance of a CAN network can be reduced signifi-
cantly.
In many cases, the CAN bit synchronization will amend a faulty configuration of
the CAN bit timing to such a degree that only occasionally an error frame is gen-
erated. In the case of arbitration however, when two or more CAN nodes simulta-
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s
e
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t neously try to transmit a frame, a misplaced sample point may cause one of the
r
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d transmitters to become error passive.
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e The analysis of such sporadic errors requires a detaile#d knowledge of the CAN
v
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o bit synchronization inside a CAN node and of the CAN nodes’ interaction on the
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u CAN bus.
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e The purpose of this paper is to describe the CAN bit synchronization algorithm
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y and the parameters which have to be considered for the proper calculation of the
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t CAN bit time.
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o Some critical cases of resynchronizations will be demonstrated by waveforms
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t simulated in the VHDL CAN Reference Model’s testbench.
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